1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a resistor structure between adjacent transistor gates on an integrated circuit (IC) product and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each transistor device comprises laterally spaced apart drain and source regions that are formed in a semiconductor substrate, a gate electrode structure positioned above the substrate and between the source/drain regions, and a gate insulation layer positioned between the gate electrode and the substrate. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region and current flows from the source region to the drain region.
Transistor devices are considered to be “active” devices in that they are switched between an “ON” state and an “OFF” state during the operation of the IC product. The circuits in an IC product also include “passive” devices, such as resistors and capacitors that are positioned in various arrangements in the circuits of the IC product so as to permit the IC product to perform its intended function. For example, resistors may be employed to reduce a voltage level or current applied to a particular portion of an integrated circuit on an IC product.
Passive devices, such as resistors, may be formed using a variety of techniques and they may be located at various locations within an integrated circuit product. As one example, some prior art IC products involved forming a resistor structure in a layer of insulating material at a location that was above the device level contacts formed on an IC product. In other applications, wherein gate structures were formed using replacement gate manufacturing techniques that involved formation of sacrificial gate electrode structures comprised of polysilicon, resistors were formed using some portions of the polysilicon sacrificial gate structures for the resistor structure. However, as the critical dimension of transistor devices and packing densities continue to decrease, there is a need to develop a process for forming resistor structures in an efficient manner that is consistent with meeting ever increasing packing densities goals while making IC products that may be reliably manufactured with acceptable levels of product yield.
The present disclosure is directed to various novel methods of forming a resistor structure between adjacent transistor gates on an integrated circuit (IC) product and the resulting novel devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.